Many high performance semiconductor packages incorporate a multilayer substrate, with an interior cavity, for interconnection with a semiconductor device. The semiconductor device is located within the interior cavity where it is electrically connected to each of a plurality of wiring layers in the multilayer substrate. Each wiring layer comprises a fiberglass laminate bonded on either side to a layer of metal, e.g., copper, defining an interconnection circuitry pattern. The interior cavity has a stepped vertical profile and each step, or bonding tier, includes bonding surfaces, or bond pads, for accepting wire bond connections from the semiconductor device.
A multilayer substrate may be produced by laminating, i.e., bonding, an assembly comprised of several wiring layers, each layer having a differently sized interior cavity or window, stacked so that the assembly has an interior cavity with a stepped vertical profile. One or more layers of adhesive, usually in the form of a sheet of woven material coated with a partially cured epoxy resin, or "pre preg," are interposed between adjacent wiring layers and bond the layers together during lamination.
One problem associated with producing such a multilayer substrate is adhesive overflow during lamination. The high temperatures and pressures of the lamination process cause the adhesive to flow from between the wiring layers onto the bonding tiers in the interior cavity. This decreases the available wire bonding surface of the bonding tiers and requires the semiconductor package manufacturers to increase the width of the bonding tiers, which in turn increases the requisite wire bond length from the semiconductor device to the bond pads. As wire bond length is inversely proportional to signal speed in the package, increasing wire bond lengths reduces signal speeds in the package. Additionally, the overall size of the resultant semiconductor package must be increased to accommodate the wider bonding tiers.
One solution proposed is to prevent adhesive overflow onto the bonding tiers by coating the adjacent surfaces of two wiring layers in the lamination assembly with a layer of epoxy resin prior to lamination. In this manner, a thinner sheet of pre preg may be used between adjacent wiring layers and the edge of the sheet may be recessed from the edge of the larger interior window of the upper wiring layer with the pre-coated epoxy resin providing adhesive material at that edge.
However, such methods require two additional processing steps as the epoxy resin must first be printed on the surfaces of the wiring layers and then cured. Also, introducing an additional material, i.e., the epoxy resin, into the lamination assembly increases the potential for cracking due to differences in the rates (coefficients) of thermal expansion among the several materials in the assembly.
Another problem associated with adhesive overflow is that the surface of the overflow adhesive on the bonding tiers tends to be rough, including cavities that may trap chemicals or moisture during subsequent processing steps and ruin the package.
Yet another problem that may be encountered in the manufacture of a high performance semiconductor package that includes a multilayer substrate is adhesion at the nonessential metal surfaces in the cavity, i.e., those metal surfaces not required for wire bonding. For example, the interior cavity of the multilayer substrate, which houses the semiconductor device, may be encapsulated for environmental protection using a liquid epoxy resin or other components may be bonded onto the cavity surface using polymer adhesives. These adhesives or encapsulants usually have a low bonding affinity for metal, e.g., the metal surfaces on the vertical edges of the wiring layers.
A further problem associated with lamination of the multilayer substrate is contamination of the metallic bonding surfaces by "resin dust." Resin dust refers to particles and fibers which dislodge from the fiberglass laminates in the wiring and adhesive layers and migrate throughout the assembly during lamination. This resin dust may adhere to the bond pads, decreasing the integrity of the ultimate electrical connection between the wire bonds on the semiconductor device and the bond pads on the package.
One solution to this problem is to attempt a "powder-free" process in which the fiberglass laminates in the wiring and adhesive layers are further cured to bond any loose particles or fibers onto the wiring and adhesive layers, thereby preventing them from dislodging and migrating during lamination. However, this curing process requires an extra heating step which may be undesirable in some manufacturing processes.
The present invention provides a way to reduce adhesive overflow onto the bonding tiers of a multilayer substrate during lamination without introducing additional materials into the substrate.
The invention also provides a smooth or micro patterned surface to adhesive exposed in the cavity of the multilayer substrate.
In addition, the invention reduces resin dust contamination of the bond pads in the cavity of the multilayer substrate during lamination.